RT8060A 1 ds8060a-00 march 2011 www.richtek.com features z z z z z 2.7v to 5.5v wide input voltage range z z z z z adjustable output voltage z z z z z 1a output current z z z z z up to 95% efficiency z z z z z 1.5mhz fixed frequency pwm operation z z z z z power good indicator z z z z z over current protection z z z z z internal sort-start z z z z z no schottky diode required z z z z z internal compensation z z z z z rohs compliant and halogen free applications z storage device : hdd/odd z wireless and dsl modems 1.5mhz, 1a high efficiency step-down converter general description the RT8060A is a current mode, high efficiency pwm step-down dc/dc converter that can support a wide input voltage range from 2.7v to 5.5v, while delivering up to 1a output current. the current mode operation provides fast transient response and eases loop stabilization. a 1.5mhz frequency operation allows the use of a smaller inductor to meet the space and height limitations handheld applications. the RT8060A is available in a sot-23-5 package. ordering information pin configurations (top view) sot-23-5 note : richtek products are : ` rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ` suitable for use in snpb or pb-free soldering processes. pgood gnd lx fb vin 4 23 5 marking information 20 = : product code dnn : date code typical application circuit RT8060A package type b : sot-23-5 lead plating system g : green (halogen free and pb free) 20=dnn 4.7f 10f vin fb gnd RT8060A lx pgood 2.2h v in v out c in l 1 5 4 3 2 c out c1 10pf 200k 200k r1 r2
RT8060A 2 ds8060a-00 march 2011 www.richtek.com function block diagram functional pin description pin no. pin name pin function 1 pgood power good indicator. 2 gnd ground. 3 lx switch node. 4 vin supply input. 5 fb feedback input. c comp rc r s1 r s2 vin lx fb uvlo & power good detector v ref slope compensation current sense osc & shutdown control current limit detector driver control logic pwm comparator error amplifier gnd pgood
RT8060A 3 ds8060a-00 march 2011 www.richtek.com absolute maximum ratings (note 1) z supply input voltage, v in ------------------------------------------------------------------------------------------ ? 0.3v to 6.5v z lx pin v oltage -------------------------------------------------------------------------------------------------------- ? 0.3v to (v in + 0.3v) z other i/o pin voltage ----------------------------------------------------------------------------------------------- ? 0.3v to 6.5v z power dissipation, p d @ t a = 25 c sot-23-5 -------------------------------------------------------------------------------------------------------------- 0.4w z package thermal resistance (note 2) sot-23-5, ja --------------------------------------------------------------------------------------------------------- 250 c/w z junction temperature range -------------------------------------------------------------------------------------- 150 c z lead temperature (soldering, 10 sec.) ---------------------------------- --------------------------------------- 260 c z storage temperature range -------------------------------------------------------------------------------------- ? 65 c to 150 c z esd susceptibility (note 3) hbm (human body mode) ---------------------------------------------------------------------------------------- 2kv mm (ma chine mode) ------------------------------------------------------------------------------------------------ 200v electrical characteristics (v in = 3.6v, t a = 25 c, unless otherwise specified) parameter symbol test conditions min typ max unit quiescent current i q -- 78 -- a reference voltage v ref 0.588 0.6 0.612 v v in rising 2 2.3 2.45 under voltage lockout threshold v uvlo hysteresis -- 0.2 -- v switching frequency f sw 1.2 1.5 1.8 mhz pgood low threshold vfb falling -- 85 -- %v ref pgood high threshold vfb rising -- 90 -- %v ref thermal shutdown temperature t sd -- 150 -- c switch on resistance, high r pfet i lx = 0.2a -- 250 -- m switch on resistance, low r nf et i lx = 0.2a -- 200 -- m peak current limit i lim 1.1 1.5 2 a output voltage line regulation v in = 2.7v to 5.5v -- 0.1 -- %/v output voltage load regulation 0a < i load < 0.6a -- 1 -- %/a recommended operating conditions (note 4) z supply input voltage ------------------------------------------------------------------------------------------------ 2.7v to 5.5 v z junction temperature range -------------------------------------------------------------------------------------- ? 40 c to 125 c z ambient temperature range -------------------------------------------------------------------------------------- ? 40 c to 85 c
RT8060A 4 ds8060a-00 march 2011 www.richtek.com note 1. stresses listed as the above ? absolute maximum ratings ? may cause permanent damage to the device. these are for stress ratings. functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. note 2. ja is measured in natural convection at t a = 25 c on a low effective thermal conductivity test board of jedec 51-3 thermal measurement standard. note 3. devices are esd sensitive. handling precaution recommended. note 4. the device is not guaranteed to function outside its operating conditions.
RT8060A 5 ds8060a-00 march 2011 www.richtek.com typical operating characteristics load transient response time (250 s/div) v in = 5.5v, i out = 50ma to 1a v out (50mv/div) i out (500ma/div) frequency vs. temperature 1.20 1.25 1.30 1.35 1.40 1.45 1.50 1.55 1.60 -50 -25 0 25 50 75 100 125 temperature (c) frequency (mhz) 1 v in = 5.5v v in = 3.6v i out = 0.5a reference voltage vs. temperature 0.570 0.575 0.580 0.585 0.590 0.595 0.600 0.605 0.610 0.615 0.620 -50 -25 0 25 50 75 100 125 temperature (c) reference voltage (v) v in = 5v, i out = 0.6a reference voltage vs. input voltage 0.570 0.575 0.580 0.585 0.590 0.595 0.600 0.605 0.610 0.615 0.620 2.8 3.3 3.8 4.3 4.8 5.3 input voltage (v) reference voltage (v) i out = 0.6a efficiency vs. load current 0 10 20 30 40 50 60 70 80 90 100 0 0.2 0.4 0.6 0.8 1 load current (a) efficiency (%) v in = 3.8v v in = 5v v in = 5.5v v out = 1.2v reference voltage vs. output current 0.570 0.575 0.580 0.585 0.590 0.595 0.600 0.605 0.610 0.615 0.620 0.0 0.2 0.4 0.6 0.8 1.0 output current (a) reference voltage (v) v buck = 12v v in = 5.5v v in = 5v v in = 4.2v
RT8060A 6 ds8060a-00 march 2011 www.richtek.com line transient response time (100 s/div) i out = 100ma v in (2v/div) v out (10mv/div) switching time (250ns/div) v in1 = 5.5v, i out = 500ma v lx (5v/div) i inductor (500ma/div) v out (20mv/div) pgood threshold vs. temperature 70% 75% 80% 85% 90% 95% 100% -50 -25 0 25 50 75 100 125 temperature (c) percent of v ref (%) 100 97 94 91 88 85 82 79 76 73 70 low to high high to low v in = 5.5v switching time (250ns/div) v in1 = 5.5v, i out = 1a v lx (5v/div) i inductor (1a/div) v out (20mv/div)
RT8060A 7 ds8060a-00 march 2011 www.richtek.com applications information the basic RT8060A application circuit is shown in typical application circuit. external component selection is determined by the maximum load current and begins with the selection of the inductor value and operating frequency followed by c in and c out . inductor selection for a given input and output voltage, the inductor value and operating frequency determine the ripple current. the ripple current i l increases with higher v in and decreases with higher inductance. out out l(max) in(max) vv l x 1 fi v ?? ?? =? ?? ?? ?? ?? ?? a smaller inductor changes its current more quickly for a given voltage drive than a larger inductor, resulting in faster transient response. a larger inductor will reduce output ripple and current ripple, but at the expense of reduced transient performance and a physically larger inductor package size. for this reason, a larger capacitor, c1, will be required for larger inductor sizes. the input regulator has an instantaneous peak current clamp to prevent the inductor from saturating during transient load or start-up conditions. the clamp is designed so that it does not interfere with normal operation at high loads and reasonable inductor ripple. it is intended to prevent inductor current runaway in case of a shorted output. the dc winding resistance and ac core losses of the inductor will also affect efficiency, and therefore available output power. these effects are difficult to characterize and vary by application. some inductors and capacitors that may be suitable for this application are listed in table below : length width height inductance rdc idc (mm) (mm) (mm) ( h) (m ) (a) p/n max. max. max. l max. max. supplier vlf5012st-1r0n2r5 5 4.8 1.2 1 50 3.3 vlf5014st-2r2m2r3 5 4.8 1.4 2.2 73 3 vlf3010a-1 3 2.8 1 2.2 120 1 vlf3012a 3 2.8 1.2 2.2 100 1 vls2010e 2.1 2.1 1 2.2 228 1 vls2012e 2.1 2.1 1.2 2.2 153 1 tdk nr6045t1r0n 6 6 4.5 1 19 4.2 cb2016t2r2m 2.2 1.8 1.8 2.2 130 1 nr6020t2r2n 6 6 2 2.2 34 2.7 nr3015 3 3 1.5 2.2 60 1.48 taiyo lps4018 3.9 3.9 1.7 3.3 80 2.2 coilcraft d53lc 5 5 3 3.3 34 2.26 db318c 3.8 3.8 1.8 3.3 70 1.55 toko we-tpc type m1 4.8 4.8 1.8 3.3 65 1.95 wurth out out l in vv i x 1 fl v ?? ?? =? ?? ?? ?? ?? having a lower ripple current reduces the esr losses in the output capacitors and the output voltage ripple. highest efficiency operation is achieved at low frequency with small ripple current. this, however, requires a large inductor. a reasonable starting point for selecting the ripple current is i l = 0.4(i max ). the largest ripple current occurs at the highest v in . to guarantee that the ripple current stays below a specified maximum, the inductor value should be chosen according to the following equation : table
RT8060A 8 ds8060a-00 march 2011 www.richtek.com out l x out 1 v i esr 8fc ?? + ?? ?? out in rms out(max) in out v v ii x 1 vv =? this formula has a maximum at v in = 2v out , where i rms = i out /2. this simple worst-case condition is commonly used for design because even significant deviations do not result in much difference. choose a capacitor rated at a higher temperature than required. several capacitors may also be paralleled to meet size or height requirements in the design. the selection of c out is determined by the effective series resistance (esr) that is required to minimize voltage ripple and load step transients, as well as the amount of bulk capacitance that is necessary to ensure that the control loop is stable. loop stability can be checked by viewing the load transient response as described in a later section. the output ripple, v out , is determined by : the output ripple is highest at maximum input voltage since i l increases with input voltage. multiple capacitors placed in parallel may be needed to meet the esr and rms current handling requirements. dry tantalum, specialpolymer, aluminum electrolytic and ceramic capacitors are all available in surface mount packages. special polymer capacitors offer very low esr but have lower capacitance density than other types. tantalum capacitors have the highest capacitance density but it is important to only use types that have been surge tested for use in switching power supplies. aluminum electrolytic capacitors have significantly higher esr but can be used in cost-sensitive applications provided that consideration is given to ripple current ratings and long term reliability. ceramic capacitors have excellent low esr characteristics but can have a high voltage coefficient and audible piezoelectric effects. the high q of ceramic capacitors with trace inductance can also lead to significant ringing. c in and c out selection the input capacitance, c in , is needed to filter the trapezoidal current at the source of the top mosfet. to prevent large ripple voltage, a low esr input capacitor sized for the maximum rms current should be used. rms current is given by : using ceramic input and output capacitors higher value, lower cost ceramic capacitors are now becoming available in smaller case sizes. their high ripple current, high voltage rating and low esr make them ideal for switching regulator applications. however, care must be taken when these capacitors are used at the input and output. when a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the input, v in . at best, this ringing can couple to the output and be mistaken as loop instability. at worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at v in large enough to damage the part. output voltage programming the resistive voltage divider allows the fb pin to sense a fraction of the output voltage as shown in figure 1. figure 1. output voltage setting out ref r1 vv(1) r2 =+ where v ref is the internal reference voltage (0.6v typ.) for adjustable voltage mode, the output voltage is set by an external resistive voltage divider according to the following equation : checking transient response the regulator loop response can be checked by looking at the load transient response. switching regulators take several cycles to respond to a step in load current. when a load step occurs, v out immediately shifts by an amount equal to i load (esr), where esr is the effective series resistance of c out . i load also begins to charge or discharge c out, generating a feedback error signal used by the regulator to return v out to its steady-state value. during this recovery time, v out can be monitored for overshoot or ringing that would indicate a stability problem. RT8060A gnd fb r1 r2 v out lx
RT8060A 9 ds8060a-00 march 2011 www.richtek.com 85% v ref 90% v ref v fb pgood figure 2. v fb and pgood comparator waveform thermal considerations for continuous operation, do not exceed absolute maximum junction temperature. the maximum power dissipation depends on the thermal resistance of the ic package, pcb layout, rate of surrounding airflow, and difference between junction and ambient temperature. the maximum power dissipation can be calculated by the following formula : p d(max) = (t j(max) ? t a ) / ja where t j(max) is the maximum junction temperature, t a is the ambient temperature, and ja is the junction to ambient thermal resistance. for recommended operating condition specifications of the RT8060A, the maximum junction temperature is 125 c and t a is the ambient temperature. the junction to ambient thermal resistance, ja , is layout dependent. for sot- 23-5 packages, the thermal resistance, ja , is 250 c/w on a standard jedec 51-3 single-layer thermal test board. the maximum power dissipation at t a = 25 c can be calculated by the following formula : p d(max) = (125 c ? 25 c) / (250 c/w) = 0.4w for sot-23-5 package the maximum power dissipation depends on the operating ambient temperature for fixed t j(max) and thermal resistance, ja . for the RT8060A package, the derating curve in figure 3 allows the designer to see the effect of rising ambient temperature on the maximum power dissipation. figure 3. derating curves for RT8060A package 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0 25 50 75 100 125 ambient temperature (c) maximum power dissipation (w) 1 single-layer pcb pgood output pgood is an open-drain output that indicates whether the output voltage is ready or not. pgood is typically pulled up to 3.3v or tied with vin. pgood is in high impedance when the voltage on fb pin exceeds the rising threshold 90% of v ref 0.6v (typ). pgood is in low impedance when the voltage on fb pin falls below the falling threshold 85% of v ref . if the voltage detector feature is not required, connect pgood to ground.
RT8060A 10 ds8060a-00 march 2011 www.richtek.com richtek technology corporation headquarter 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 fax: (8863)5526611 information that is provided by richtek technology corporation is believed to be accurate and reliable. richtek reserves the ri ght to make any change in circuit design, specification or other related things if necessary without notice at any time. no third party intellectual property inf ringement of the applications should be guaranteed by users when integrating richtek products into any application. no legal responsibility for any said applications i s assumed by richtek. richtek technology corporation taipei office (marketing) 5f, no. 95, minchiuan road, hsintien city taipei county, taiwan, r.o.c. tel: (8862)86672399 fax: (8862)86672377 email: marketing@richtek.com outline dimension a a1 e b b d c h l sot-23-5 surface mount package dimensions in millimeters dimensions in inches symbol min max min max a 0.889 1.295 0.035 0.051 a1 0.000 0.152 0.000 0.006 b 1.397 1.803 0.055 0.071 b 0.356 0.559 0.014 0.022 c 2.591 2.997 0.102 0.118 d 2.692 3.099 0.106 0.122 e 0.838 1.041 0.033 0.041 h 0.080 0.254 0.003 0.010 l 0.300 0.610 0.012 0.024
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